1. Field of the Invention
The present invention relates to a voltage-controlled oscillator circuit and a PLL circuit, and particularly to a differential type voltage-controlled oscillator circuit and a PLL circuit including the same.
2. Description of the Related Art
In radio communications using portable telephones and the like, serial communications through various cables, systems for reproducing digitally recorded data from disk media (read channels), and the like, a PLL (Phase-Locked Loop) circuit is widely used to generate an oscillating signal with a high spectrum precision and generate a clock signal locked in frequency and phase to a data signal.
Recently, there has been a demand for increase in the speed of oscillating signals and clock signals, and there has been a desire for higher-performance PLL circuits.
One of indexes of performance called for of PLL circuits is the precision of an output signal. The precision of the output signal is decreased by thermal noise and various noises inherent in elements. Therefore suppression of this decrease is desired. As an index for evaluating this precision, indexes referred to as jitter performance and phase noise are widely used.
Main factors in jitter and phase noise include noise of a voltage-controlled oscillator (VCO) provided within a PLL circuit. The jitter performance of the PLL circuit can be improved by reducing the noise itself of the VCO.
VCOs are generally classified roughly into two types, that is, LCVCOs and ring VCOs according to the structures of the VOCs. LCVCOs generally have superior jitter performance. However, ring VCOs are widely used in applications where a jitter performance requirement is not so severe because of advantages of the ring VCO having a wide variable frequency range, being able to output a plurality of output signals different from each other in phase, and requiring no inductor, for example. Therefore improvement of the jitter performance of the ring VCO is desired to extend applications of the ring VCO.
Accordingly, description in the following will be made focusing on a differential type ring VCO.
FIG. 11 is a schematic diagram showing a differential type ring VCO in related art.
The ring VCO 90 includes a cascade connection of same VCO cells C91, C92, . . . , C9(n−1), and C9n in N stages (N VCO cells). When the number N of stages is an even number, the ring VCO 90 also includes an inverting unit for inverting differential signal lines. This inverting unit is unnecessary when the number N of stages is an odd number.
The oscillation frequency (hereinafter f0) of the ring VCO is expressed by a delay time TD of the VCO cells and the number N of stages of the VCO cells as in Equation (1).f0=½N·TD   (1)
The output differential signals of adjacent VCO cells have a phase difference of π/N [rad] when N is an even number, and have a phase difference of 2π/N [rad] when N is an odd number.
The internal configuration of each VCO cell will next be described. However, since the internal configurations of the VCO cells C91, C92, . . . , C9(n−1), and C9n are similar to each other, the VCO cell C91 will be described as a representative.
FIG. 12 is a circuit diagram showing an equivalent circuit of the VCO cell shown in FIG. 11.
The VCO cell C91 includes loads R91 and R92, NMOS transistors M91 and M92, and a constant-current source I.
The NMOS transistors M91 and M92 form a differential pair (source-coupled pair). The drain of the NMOS transistor M91 is connected with the load R91. The drain of the NMOS transistor M92 is connected with the load R92. The gate of the NMOS transistor M91 is connected with an input terminal In+ to which a signal V+ is input. The gate of the NMOS transistor M92 is connected with an input terminal In− to which a signal V− is input.
An output terminal Out− is connected between the drain of the NMOS transistor M91 and the load R91. An output terminal Out+ is connected between the drain of the NMOS transistor M92 and the load R92.
The opposite sides of the loads R91 and R92 from the NMOS transistor M91 and the NMOS transistor M92 are each connected to a voltage source VDD.
The sources of the NMOS transistor M91 and the NMOS transistor M92 are connected to the constant-current source I for outputting a constant current Itail90 via a tail node (node) N90.
The NMOS transistors M91 and M92 generally have nonlinear characteristics. For example, the characteristics of an ideal NMOS transistor conform to a square equation expressed by Equation (2).IDS=K·(VGS−VT)   (2)
where IDS is a drain-to-source current of the NMOS transistor, K is a constant determined by the size of the NMOS transistor, VGS is a gate-to-source voltage, and VT is a threshold voltage. A common signal VC and an oscillating signal VD obtained by converting a signal V+ and a signal V− as a positive differential input signal and a negative differential input signal into a common component and a differential component are expressed by Equation (3).
                                          V            C                    =                                                    V                +                            +                              V                -                                      2                          ,                              V            D                    =                                                    V                +                            ⁢                              V                -                                      2                                              (        3        )            
The voltage Vtail90 of the tail node N90 satisfies a relation of Equation (4) obtained from Equation (2) and Equation (3).
                              V                      tail            ⁢                                                  ⁢            90                          =                              V            C                    -                      V            T                    -                                                                      I                                      tail                    ⁢                                                                                  ⁢                    90                                                                    2                  ⁢                  K                                            -                              V                D                2                                                                        (        4        )            
As is understood from Equation (4), the voltage Vtail90 vibrates at a frequency twice that of the differential oscillating signal VD, that is, a frequency 2f0. Incidentally, the vibration of the voltage Vtail90 at the frequency 2f0 will hereinafter be referred to as the “2f0 vibration of the voltage Vtail”. This is qualitatively understood as follows. When the differential signal VD90 (VD) vibrating in a sinusoidal manner becomes large while the common signal VC90 (VC) of the NMOS transistors M91 and M92 is fixed, the gate voltage of the NMOS transistor M91 increases, and the gate voltage of the NMOS transistor M92 decreases by an amount corresponding to the increase. However, because of the square characteristics of the NMOS transistors, a certain amount of increase in the gate-to-source voltages VGS90 (VGS) of the NMOS transistors M91 and M92 cause a greater current change than the same amount of decrease.
FIG. 13 is a graph showing the 2f0 vibration of the voltage at the tail node.
An overall current value is fixed at a constant value by the current source, and consequently an amount of change in the NMOS transistors M91 and M92 is adjusted by increase in the voltage Vtail90. The same is true for a case where the gate voltage of the NMOS transistor M92 increases. Hence, the voltage Vtail90 vibrates at a frequency twice the oscillation frequency.
However, the square characteristic of the NMOS transistor in a triode region (non-saturation region) in which a drain-to-source voltage VDS is lower than a voltage (VGS−VT) is expressed by Equation (5).IDS=K·{2·(VGS−VT)2·VDS−VDS2}  (5)
An amplification factor gm of the NMOS transistor decreases in the triode region. That is, the gradient of an output waveform becomes gentle.
FIG. 14 is a graph showing the output waveform resulting from the 2f0 vibration of the voltage at the tail node.
The above-described 2f0 vibration of the voltage Vtail distorts the output signal of the VCO cell C91. Specifically, as shown in FIG. 13, the voltage Vtail becomes highest when the signal V+ or the signal V− is smallest, the NMOS transistors M91 and M92 alternately enter the triode region, and the amplification factor gm, that is, the gradient of the output waveform is decreased. As a result, a frequency 2f0 component and other distortion components occur in the output signal of the VCO cell C91. Hence, a phase noise as a ratio between signal strength at a frequency f0 and signal strength at a frequency adjacent to the frequency f0 deteriorates. In addition, a component of the vibration of the frequency 2f0 causes harmonic distortion. Also, the amplitude of the output waveform is decreased.
It is known that a distorted oscillation waveform degrades the phase noise and jitter performance of the VCO due to the following causes (1) and (2) (see Non-Patent Document 1, for example).    (1) Due to a decrease in the peak-to-peak voltage of the output waveform, even when an amount of noise of a noise source is fixed, an amount of conversion of the noise source to phase noise increases.    (2) Due to asymmetry of the output waveform, an amount of conversion of various noise sources to phase noise increases, and in particular, effects of flicker (1/f) noise significantly increase.
In related art, it is known that the vibration of the voltage Vtail makes oscillating operation unstable (see Patent Document 1).
FIG. 15 is a block diagram showing the configuration of another ring VCO in the past.
Incidentally, the same reference numerals are used to denote the same parts as in the ring VCO 90, and description thereof will be omitted.
In the ring VCO 91, an NMOS transistor is connected between each of tail nodes of VCO cells C91, C92, . . . , C9(n−1), and C9n and a ground (GND) terminal, and a replica cell Cr that has the same structure as the VCO cells C91, C92, . . . , C9(n−1), and C9n but is not supplied with signals is provided. Voltages at the tail nodes of all the VCO cells are controlled by an operational amplifier (not shown) so as to be equal to a reference tail node voltage of the replica cell.
[Patent Document 1]
Japanese Patent Laid-open No. 2001-326560
[Non-Patent Document 1]
“A general theory of phase noise in electrical oscillators,” IEEE J. Solid-State Circuits, vol. 33, pp. 179-194, February 1998